The present invention relates to a method of manufacturing a semiconductor device wherein a multilayered structure is etched to form a pattern therein. The invention is particularly useful in etching a plurality of silicon-based layers at high etch rates and at a high etch rate ratio to an underlying dielectric layer using a chlorine and oxygen etch chemistry.
The escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
Conventional semiconductor devices comprise a substrate and various structural layers thereon, in which individual circuit components are formed. The formation of various circuit components is partly accomplished by employing conventional photolithographic techniques to form a mask on the substrate and further etching through openings in the photoresist-mask to one or more layers of the substrate. Practically all semiconductor devices incorporate a multitude of such patterning and etching processes.
An exemplary memory cell 8, of a conventional memory device, is depicted in FIG. 1A, viewed in a cross-section through the bit line. Memory cell 8 includes a doped substrate 12 having a top surface 11, and a source region 13a and a drain region 13b formed by selectively doping regions of substrate 12. A tunnel oxide 15 separates a floating gate 16 from substrate 12. An interpoly dielectric 24 separates floating gate 16 from a control gate 26. Floating gate 16 and control gate 26 are each electrically conductive and typically formed of polycrystalline silicon (polysilicon).
On top of control gate 26 is a silicide layer 28, which acts to increase the electrical conductivity of control gate 26. Silicide layer 28 is typically a tungsten silicide (e.g., WSi2), that is formed on top of control gate 26 prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell 8 can be programmed, for example, by applying an appropriate programming voltage to control gate 26. Similarly, memory cell 8 can be erased, for example, by applying an appropriate erasure voltage to source 13a. When programmed, floating gate 16 will have a binary charge corresponding to either a 1 or 0. By way of example, floating gate 16 can be programmed to a binary 1 by applying a programming voltage to control gate 26, which causes an electrical charge to build up on floating gate 16. If floating gate 16 does not contain a threshold level of electrical charge, then floating gate 16 represents a binary 0. During erasure, the charge is removed from floating gate 16 by way of the erasure voltage applied to source 13a. 
FIG. 1B depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in FIG. 1A). In FIG. 1B, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate 12. For example, FIG. 1B shows a portion of a floating gate 16a associated with a first memory cell, a floating gate 16b associated with a second memory cell, and a portion of floating gate 16c associated with a third memory cell. Floating gate 16a is physically separated and electrically isolated from floating gate 16b by a field oxide (FOX) 14a. Floating gate 16b is separated from floating gate 16c by a field oxide 14b. Floating gates 16a, 16b, and 16c are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate 12, tunnel oxide 15, and field oxides 14a and 14b. Interpoly dielectric layer 24 has been conformally deposited over the exposed portions of floating gates 16a, 16b, and 16c and field oxides 14a and 14b. Interpoly dielectric layer 24 isolates floating gates 16a, 16b and 16c from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate 26. Interpoly dielectric layer 24 typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
The continued shrinking of the memory cells, and in particular the basic features depicted in the memory cells of FIGS. 1A and 1B, place a burden on the fabrication process to deposit and subsequently pattern a layer stack to form a floating gate/control gate structure, without creating deleterious effects within the resulting memory cells.
Of particular importance in memory devices is the formation and dimensions of the gate electrode. Gate dimensions are critical since the gate electrode controls the flow of electrons and is vital to proper device operation. As described above, a gate electrode is formed by depositing a polysilicon film at a uniform thickness and by subsequent deposition of necessary device layers with further processing steps thereto. The polysilicon layer employed in the control gate is typically deposited at a thickness of about 1500 xc3x85 which is greater than the thickness of the corresponding polysilicon layer in the floating gate. The greater thickness of the control gate is necessary to compensate for process limitations in the formation of a memory stack structure.
A semiconductor substrate having a conventional memory stack 10 is shown in FIG. 2. The memory stack comprises a plurality of layers including a tunnel oxide layer 15 overlying substrate 12, a first polysilicon layer 16 on tunnel oxide 15, an ONO layer 24 on polysilicon layer 16, a second polysilicon layer 26 on ONO layer 24, and a silicide layer 28 on polysilicon layer 26. The memory stack also includes a polysilicon cap layer 30 overlying silicide layer 28 and a silicon oxynitride layer 32 on polysilicon cap layer 30.
FIG. 3 illustrates a flow diagram employing a conventional etch process in the preparation of memory stack 10 of FIG. 2. The method begins in step 40, where the multi-layer semiconductor substrate having a silicon oxynitride top layer is covered with a photoresist layer. The photoresist layer is then patterned in step 42 to form a photoresist mask exposing select regions of the underlying silicon oxynitride layer. The semiconductor substrate is then inserted into an oxide etch chamber in step 44, and an oxide etching operation is performed to etch the exposed regions of the underlying silicon oxynitride layer to expose the underlying poly cap layer. The semiconductor substrate is then moved in step 46 from the oxide etch chamber to a polysilicon etch chamber, where a polysilicon etch process is performed on poly cap layer 30 and silicide layer 28.
Conventional etch chemistry and equipment requires that a high selectivity to the silicide be achieved so that all of silicide layer 28 can be cleared while the underlying polysilicon layer 26 remains intact. However, achieving a high selectivity is difficult using conventional processes particularly since the silicide and polysilicon layers have similar etching properties. Thus, to ensure the complete etching of silicide layer 28 requires the partial etching of underlying polysilicon 26. The resulting structure is depicted in FIG. 4, where the numerals represent layers as described for FIG. 2 (the patterned photoresist layer is not shown for illustrative convenience).
Further, should polysilicon underlayer 26 be erroneously removed during etching of silicide layer 28, conventional silicide etch processes would rapidly etch underlying oxide layer 24 resulting in deleterious pitting therein. The inability to achieve high selectivity to polysilicon during etching of silicide has conventionally been compensated for by providing a thick polysilicon layer. Conventionally, silicide layers are etched employing a fluorine source and a substrate temperature of 65xc2x0 C. to yield a selectivity of silicide to polysilicon of 1:1. However, the fluorine chemistry rapidly etches oxides.
Subsequent to etching the silicide layer, polysilicon layer 26 is etched in step 48. The etch process of step 48 requires a separate etching step with a different etch chemistry such that a higher selectivity to the underlying oxide can be achieved. The etch chemistry employed in step 48 must have a higher selectivity to the underlying oxide than the silicide etch chemistry employed in step 46 otherwise the same pitting problem would occur.
Hence, conventional techniques for etching silicon-based layers requires at least a two step process of first etching a poly cap and silicide layer to an underlying polysilicon layer and a second, separate etching step consisting of different etching chemistry and parameters to etch the polysilicon layer to an underlying oxide layer. Further, a high selectivity to polysilicon is required during the first silicide etch to avoid removing the underlying polysilicon and deleteriously affecting the oxide layer. Since this high selectivity is difficult to achieve, a thick polysilicon layer is required to compensate for over etching the silicide layer thereby resulting in a thicker control gate electrode.
Accordingly, there is a continuing need for improved processes for manufacturing semiconductor substrates having multiple silicon-based layers that minimize etching steps and a continuing need for fabrication processes that permit improved control over the dimensions of gate electrodes.
There is a need for manufacturing a semiconductor device by etching a plurality of silicon layers to reduce process variation and processing steps.
There is also a need for a semiconductor substrate with a control gate having a reduced thickness.
According to the present invention, the foregoing and other objects are achieved in part by a method of etching a semiconductor substrate having a plurality of silicon-based layers. The method comprises etching the silicon-based layers in an etching chamber by exposing the semiconductor substrate to a mixture of chlorine (Cl2) and oxygen (O2). The use of Cl2 and O2 in a polysilicon etch environment permits etching of the plurality of silicon layers in a single step avoiding a separate polysilicon etching step for the formation of a control gate electrode. Further, since the Cl2 and O2 chemistry has good selectivity to dielectric materials, it avoids pitting of a underlying dielectric layer which can result with conventional silicide etching techniques.
Another aspect of the present invention is a method of etching a semiconductor substrate having a plurality of silicon-based layers overlying the semiconductor substrate to achieve a thinner control gate electrode. The method comprises etching the plurality of silicon-based layers in a single polysilicon etch environment to form a control gate electrode of no greater than about 800 xc3x85 thick. The Cl2 and O2 chemistry permit etching a plurality of silicon-based layers comprising a silicide layer over a polysilicon layer in a single step, thus avoiding the need to deposit a thick polysilicon underlayer to compensate for over-etching of the silicide layer. A semiconductor device comprising a polysilicon layer having a thickness no greater than about 800 xc3x85 can thus be fashioned.
Additional advantages of the present invention will become readily apparent to those having ordinary skill in the art from the following detailed description, wherein the embodiments of the invention are described, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.